AXI4-Lite Slave Verilog Generator

This tool generates a Verilog module for an AXI4-Lite slave interface. You can specify the number of read/write and read-only registers.

Fill in the form below to generate the Verilog code. The generated code will be displayed below the form.

Note: The generated code is a template and may require further modifications to fit your specific design requirements.

For more information about the AXI4-Lite protocol, refer to the AXI4-Lite Specification.

Module Name:

Number of RW Registers:

Number of RO Registers:

Generated Verilog Code

Tool created for research purposes. It is not intended for production use. Please review the generated code before using it in any project.

v1.0